Digital systems and modules are ubiquitous, serving for a variety of purposes, including data processing, communication and control. In the context of the present specification, a digital system or module may be any of a wide range of sizes and packages, from a single semiconductor chip, through a multiple chip board or module to an assembly of boards or modules. Any of these may form a part of a more general system, such as an electronic system, an electrical power system, an appliance, a vehicle, etc.
Typically a clock signal is provided within the digital system to which various other signals are synchronized or from which they are derived. A clock signal typically consists of a train of pulses at a constant frequency. In the following description a clock signal will be simply referred to as a clock. Often there are provided within a system one or more additional clocks, generated independently of the first clock, although in many cases they are related to, derived from, or synchronized with, the first clock. Any of the clocks may be generated, by respective clock generators, within the system under consideration or outside it.
Usually the first clock has a highly stable frequency and is therefore often called a reference clock, while the other clocks, referred to as ancillary clocks, are generated in a manner that causes their respective frequencies to be inherently less stable. Often, the frequency of an ancillary clock is much higher than that of the reference clock. Typically, a high frequency ancillary clock is generated under some relation to the reference clock. Two well known means for such generation are the Phase Locked Loop (PLL) and the Frequency Multiplier (Fmul).
Due to various causes, the frequency of an ancillary clock may not always be stable, even if the clock is generated in synchrony with the reference clock. This is particularly true for frequencies much higher than that of the reference clock. Two particular effects are often noticeable in synchronous types of clock generators: (1) short-term fluctuations, namely those occurring between moments of synchronization, and (2) inherent drift. The meaning of inherent drift is that the frequency tends to drift away from its nominal value and is kept at that value only by the effect of the synchronization. If the tendency to drift becomes strong enough, the situation may become unstable and the synchronization may become ineffective or erroneous.
It is often desirable to detect frequency drift tendencies before they cause drastic effects. In other cases it is often desirable to detect frequency deviations exceeding certain given threshold values. The need for such detection may arise during production of chips that contain ancillary clock generators, for example, in order to possibly control production parameters or to reject a chip when unacceptable frequency deviations have been detected. A need for such detection may similarly arise during normal usage of the digital system, for example, in order to warn of an actual or impending malfunction due to frequency deviations. For the case of detection during production, it is further desirable that the means for detection be provided on the same chip as the clock generator under consideration, thus avoiding the need for a special test setup.
U.S. Pat. No. 5,633,609 to Duncan discloses an internal monitor circuitry that detects whether a clock signal is present at its input. The circuit does not, however, detect the frequency of the clock signal, nor any deviations of the frequency from a given value. U.S. Pat. No. 5,497,110 to Smith discloses a frequency monitor and error detector circuit that compares an input alternating current (ac) signal with a reference frequency, which is much higher than that of the alternating current (ac) signal. The times of zero transitions of the alternating current (ac) signal are compared with those of the nearest cycles of the reference frequency in order to yield a measure of frequency deviation, which is processed in a logic circuit to obtain a go/no-go decision.
The circuitry of the Smith patent includes an inherently analog circuit and is thus not very suitable for realization on a digital integrated circuit (IC) chip. Furthermore, the Smith patent is directed to electric power frequencies and is not suitable for the high frequencies prevalent in modern digital systems, to which the present invention is directed. Moreover, the circuitry of the Smith patent is relatively complex and thus may not be economical.
Therefore there is a need in the art for a compact on-chip digital circuit for monitoring the frequency of any clock present on the integrated circuit chip.